G. Pape, B. Wintermann, L. Jungemann, M. Lass, M. Meyer, H. Riebler, and C. Plessl: AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference, 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Kumamoto, Japan, May 26-28. 2025.

L. Jungemann, B. Wintermann, H. Riebler, and C. Plessl: FINN-HPC: Closing the Gap for Energy-Efficient Neural Network Inference on FPGAs in HPC, 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Kumamoto, Japan, May 26-28. 2025.

A. H. Hadipour, A. Jafari, M. Awais, and M. Platzner: A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation, IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Lyon, France, May 5-7, 2025. (Received Best Student Paper Award)

A. Jafari and M. Platzner: Ultra-Low Latency and Extreme-Throughput Echo State Neural Networks on FPGA, 21st International Symposium on Applied Reconfigurable Computing (ARC), Seville, Spain, April 9-11, 2025.

L. Jungemann, B. Wintermann, H. Riebler, and C. Plessl: Neural Network Inference in High-Performance Computing: Closing the Gap for FINN based Reconfigurable Accelerators, 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (ISFPGA), Monterey, USA, February 27-March 1, 2025.

C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, and H. Giefers: FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers, 2024 International Conference on Field Programmable Technology (ICFPT), Sydney, Australia, December 10-12, 2024.

F, Jentzsch: Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML, PhD Forum, 33rd International Conference on Field-Programmable Logic and Applications (FPL), Gothenburg, Sweden, September 04-08, 2023.

F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, and M. Platzner: RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures, IEEE Micro 42 (2022), 125-133.